Design Verification Engineer
Meta

Meta's Reality Labs (RL) focuses on delivering Meta's vision through Augmented Reality (AR). Compute power requirements of Augmented Reality require custom silicon. Meta RL Silicon team is driving the state-of-the-art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design and verifications skills to implement the testing infrastructure to validate new core IP or SoC implementations. You will work closely with researchers, architects and designers in creating test bench requirements and test cases for multiple state of the art IPs or SoCs.

Design Verification Engineer Responsibilities:

• Work with researchers and architects defining verification plans for each of the different core IP or SoCs.
• Define and track detailed test plans for the different modules and top levels.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
• Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry.

Minimum Qualifications:

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• 3+ years of hands-on experience in Verilog, SystemVerilog, C/C++ based verification and UVM methodology.
• 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
• Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
• Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.

Preferred Qualifications:

• Experience in development of UVM based verification environments from scratch.
• Experience with Design verification of Data-center applications like Video, AI/ML and Networking designs.
• Experience with revision control systems like Mercurial(Hg), Git or SVN.
• Experience with low power design.
• Experience working across and building relationships with cross-functional design, model and emulation teams.
• Track record of 'first-pass success' in ASIC development cycles.
• Master's degree in Computer Science, Computer Engineering, or a related field.

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